Integration of Analog and Discrete Synchronous Design

The synchronous family of languages (Lustre, Esterel, Signal , Statecharts) provide a great deal of support for verifying a control program at the design and compilation stage. However, a common aspect of embedded systems is that signiicant properties of the system can not be veriied by formally analysing the controller (software) on its own. To analyse the system one requires to state and document assumptions on the environment. Furthermore, proving timeliness properties necessitates justifying a sampling interval and relating the synchronous step to metric time. Support for these activities is generally missing from current formal methods tools. In this paper we exploit simulation models { based on physical modelling of the environment { together with theorem proving, to prove properties of a closed loop system. We report on the work in progress on a case study provided by Saab Aerospace where deductive tools such as NP-Tools and simulation environments such as MATRIXx-SystemBuild are jointly used for verifying designs in Statecharts or programs in Lustre. The case study treats temperature and ow control in a climatic chamber.